Analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are widely used in a range of equipment.
An increasing drive to integrate more functionality onto integrated circuits (ICs) has led to integrated circuits having a higher density layout and the introduction of IC manufacturing technologies with smaller geometries.
While high density, small geometry, manufacturing techniques can be tolerated by digital signals, they are not so well suited to analog signals. One solution to this is to partition those parts of an IC which process analog signals from those parts which process digital signals. This allows an analog ‘front end’ section to be formed using a relatively large manufacturing geometry and a digital ‘back end’ section to be formed using a smaller manufacturing geometry. The analog front end and digital back end can be formed on separate ICs which are connected to one another via a bus.
When an analog to digital converter is partitioned in this way, and the analog front end has a multi-bit converter, i.e., a converter which resolves an analog input signal into a multi-bit digital output signal, this requires the interface between the analog front end and digital back end to have a number of separate connections to accommodate the multi-bit signal. This incurs a penalty in package pin count, since it demands a wide data bus, and can also incur a penalty in signal performance due to more switching data outputs. An alternative solution is to convert the multi-bit signal into serial format. However, parallel to serial conversion requires a higher clock rate which may not be readily available and, even where it is available, may degrade performance.
The present invention seeks to provide an improved way of interconnecting the analog and digital sections of analog-to-digital and digital-to-analog converters.